Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices having regions for forming complementary field effect transistors and regions for forming bipolar transistors and a method of manufacturing the same, and more particularly, to a structure of a Bi-CMOS gate array having a basic cell structured by combining CMOS transistors and a bipolar transistor and a method of manufacturing the same.
Description of the Background Art
A gate array has gates referred to as basic cells arranged regularly (in array) on a LSI chip, and is a LSI manufactured by means semi-customized and designed by making full use of CAD by remarkably standardizing design, development and a manufacturing step of a custom LSI. The gate array has been improved and developed to have higher performance and to be highly functional since the beginning of 1970's when it had been made into practice because in the gate array, although a chip size is increased as compared with that of a full-custom LSI, a time period required for the development and manufacturing cost can be reduced.
In recent years, a so-called Bi-CMOS gate array is proposed which combines a bipolar transistor and CMOS transistors, as a circuit capable of operating at a high speed and consuming less power.
FIG. 1 is a schematic plan view showing a structure of a master chip of a conventional gate array. Basic cells 300 are aligned laterally in an input/output buffer region 100. The laterally aligned basic cells 300 constitute a basic cell column 200. An interconnection for connecting the basic cells 300 is provided by a slicing step. In a gate array, an interconnection lattice is usually provided for making interconnections on/between the basic cells 300 by an automatic interconnection disposing method. Each interconnection is made in accordance with this interconnection lattice.
FIG. 2A is a diagram showing a structure of a plane arrangement of a basic cell 300 in a Bi-CMOS gate array in such a gate array as described above. The basic cell 300 is comprised of an n-MOS transistor region 310, a p-MOS transistor region 320 and a bipolar transistor region 330. FIG. 2B shows an intersection of the bipolar-CMOS gate array disclosed in "A SUBNANOSECOND LOW POWER ADVANCED BIPOLAR-CMOS GATE ARRAY", International Conference on Computer Design, 1984, pp. 428-433, which corresponds to an intersection taken along a line IIB--IIB of FIG. 2A. Referring to FIG. 2B, the n-MOS transistor region 310, the p-MOS transistor 320 and the bipolar transistor region 330 are formed on a p type semiconductor substrate. The n-MOS transistor region 310 has source/drain regions 312/313 formed spaced apart from each other and agate electrode 311 formed thereon through an insulation film. The p-MOS transistor region 320 has source/drain regions 322/323 formed spaced apart from each other and agate electrode 321 formed thereon through an insulation film. The bipolar transistor region 330 has a collector region 331, an emitter region 332 and a base region 333 formed so as to junction therebetween. As the foregoing, the n-MOS transistor region 310, the p-MOS transistor 320 and the bipolar transistor region 330 are formed separately from each other through isolation regions 350.
According to the above described article, by using a Bi-CMOS gate array to constitute, for example, a logic circuit such as a two-input NAND circuit, a bipolar transistor is operated complementarily only during a transition period when a logic gate is changing, whereby none of unnecessary current flows in a normal state, so that a logic circuit can be formed which maintains consumed current as low as that of a CMOS gate array and operates at a high speed.
However, formation of a bipolar transistor region in addition to the MOS transistor region causes the number of elements to be increased, thereby reducing the degree of integration of the gate array chip. In particular, in a gate array the reduction of the degree of integration becomes more marked due to a bipolar transistor region formed separately in order to arrange basic cells in an array. This is clear from that, as shown in FIG. 2A, while in a conventional CMOS gate array, a basic cell is comprised of an n-MOS transistor region and a p-MOS transistor region, in the Bi-CMOS gate array the basic cell 300 is comprised of the n-MOS transistor region 310, the p-MOS transistor region 320 and the bipolar transistor region 330. Namely, even if a logic circuit capable of operating at a high speed and consuming less power can be structured by Bi-CMOS gate arrays, the degree of integration is reduced due to the increase of the number of elements in the bipolar transistor region.